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PD - 94520
AUTOMOTIVE MOSFET
Benefits

IRF1302S IRF1302L
HEXFET(R) Power MOSFET
D
Advanced Process Technology Ultra Low On-Resistance Dynamic dv/dt Rating 175C Operating Temperature Fast Switching Repetitive Avalanche Allowed up to Tjmax
G
VDSS = 20V RDS(on) = 4.0m
S
ID = 174A
Description
Specifically designed for Automotive applications, this Stripe Planar design of HEXFET(R) Power MOSFET utilizes the lastest processing techniques to achieve extremely low on-resistance per silicon area. Additional features of this design are a 175C junction operating temperature, fast switching speed and improved repetitive avalanche rating. These benefits combine to make this design an extremely efficient and reliable device for use in Automotive applications and a wide variety of other applications.
D2Pak IRF1302S
TO-262 IRF1302L
Absolute Maximum Ratings
Parameter
ID @ TC = 25C ID @ TC = 100C IDM PD @TC = 25C VGS EAS IAR EAR dv/dt TJ TSTG Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds
Max.
174 120 700 200 1.4 20 350 See Fig.12a, 12b, 15, 16 TBD -55 to + 175 300 (1.6mm from case )
Units
A W W/C V mJ A mJ V/ns C
Thermal Resistance
Parameter
RJC RJA Junction-to-Case Junction-to-Ambient (PCB mount)
Typ.
--- ---
Max.
0.74 40
Units
C/W
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1
07/16/02
IRF1302S/IRF1302L
Electrical Characteristics @ TJ = 25C (unless otherwise specified)
V(BR)DSS
V(BR)DSS/TJ
RDS(on) VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf LD LS Ciss Coss Crss Coss Coss Coss eff.
Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Drain Inductance Internal Source Inductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Output Capacitance Output Capacitance Effective Output Capacitance
Min. 20 --- --- 2.0 59 --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- ---
Typ. --- 0.021 3.3 --- --- --- --- --- --- 79 18 31 28 130 47 16 4.5 7.5 3600 2370 520 5710 2370 3540
Max. Units Conditions --- V VGS = 0V, ID = 250A --- V/C Reference to 25C, ID = 1mA 4.0 m VGS = 10V, ID = 104A 4.0 V VDS = 10V, ID = 250A --- S VDS = 15V, ID = 104A 20 VDS = 20V, VGS = 0V A 250 VDS = 16V, VGS = 0V, TJ = 150C 200 VGS = 20V nA -200 VGS = -20V 120 ID = 104A 27 nC VDS = 16V 46 VGS = 10V --- VDD = 11V --- ID = 104A ns --- RG = 4.5 --- VGS = 10V D Between lead, --- 6mm (0.25in.) nH G from package --- and center of die contact S --- VGS = 0V --- pF VDS = 25V --- = 1.0MHz, See Fig. 5 --- VGS = 0V, VDS = 1.0V, = 1.0MHz --- VGS = 0V, VDS = 16V, = 1.0MHz --- VGS = 0V, VDS = 0V to 16V
Source-Drain Ratings and Characteristics
IS
ISM
VSD trr Qrr ton
Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse RecoveryCharge Forward Turn-On Time
Min. Typ. Max. Units
Conditions D MOSFET symbol --- --- 174 showing the A G integral reverse --- --- 700 S p-n junction diode. --- --- 1.3 V TJ = 25C, IS = 104A, VGS = 0V --- 66 100 ns TJ = 25C, IF = 104A --- 130 200 nC di/dt = 100A/s Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
2
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IRF1302S/IRF1302L
10000
VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP
10000
ID, Drain-to-Source Current (A)
1000
ID, Drain-to-Source Current (A)
1000
VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP
100
100
4.5V
10
10
4.5V 20s PULSE WIDTH Tj = 25C
20s PULSE WIDTH Tj = 175C
1
1 0.1 1 10 100
0.1
1
10
100
VDS, Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000.00
2.0
I D = 174A
ID, Drain-to-Source Current ()
T J = 175C
RDS(on) , Drain-to-Source On Resistance
1.5
100.00
(Normalized)
1.0
0.5
T J = 25C VDS = 15V
10.00 4.0 5.0
20s PULSE WIDTH
6.0 7.0
V GS = 10V
0.0 -60 -40 -20 0 20 40 60 80 100 120 140 160 180
VGS, Gate-to-Source Voltage (V)
TJ , Junction Temperature
( C)
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance Vs. Temperature
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3
IRF1302S/IRF1302L
100000
12
VGS = 0V, f = 1 MHZ Ciss = C + Cgd, C gs ds SHORTED Crss = C gd Coss = C + Cgd ds
VGS , Gate-to-Source Voltage (V)
I D = 104A
VDS = 16V
10
C, Capacitance(pF)
10000
7
Ciss Coss
1000
5
Crss
2
100 1 10 100
0 0 20 40 60 80 100
VDS, Drain-to-Source Voltage (V)
QG, Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage
1000
10000 OPERATION IN THIS AREA LIMITED BY R DS(on)
100
TJ = 175 C
ID , Drain-to-Source Current (A)
1000
I SD , Reverse Drain Current (A)
10
100
100sec 1msec
TJ = 25 C
1
10 Tc = 25C Tj = 175C Single Pulse 1 1 10
10msec
V GS = 0 V
0.1 0.2 0.7 1.2 1.7 2.2
V SD ,Source-to-Drain Voltage (V)
100
VDS , Drain-toSource Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
4
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IRF1302S/IRF1302L
175
LIMITED BY PACKAGE
VDS VGS
RD
131
RG 10V
D.U.T.
+
ID , Drain Current (A)
-VDD
88
Pulse Width 1 s Duty Factor 0.1 %
Fig 10a. Switching Time Test Circuit
44
VDS 90%
0 25 50 75 100 125 150 175
TC , Case Temperature
( C)
Fig 9. Maximum Drain Current Vs. Case Temperature
10% VGS
td(on) tr t d(off) tf
Fig 10b. Switching Time Waveforms
1
(Z thJC )
D = 0.50
0.20
Thermal Response
0.1
0.10 P DM SINGLE PULSE (THERMAL RESPONSE) t1 t2 Notes: 1. Duty factor D = 2. Peak T t1/ t 2 +TC 1
0.05
0.02 0.01
J = P DM x Z thJC
0.01 0.00001
0.0001
0.001
0.01
0.1
t1, Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRF1302S/IRF1302L
700
15V
TOP
ID 43A 74A 104A
RG
20V
D.U.T
IAS tp
EAS , Single Pulse Avalanche Energy (mJ)
VDS
L
DRIVER
560
BOTTOM
+ V - DD
420
A
0.01
280
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS tp
140
0 25 50 75 100 125 150 175
Starting Tj, Junction Temperature
( C)
I AS
Fig 12b. Unclamped Inductive Waveforms
QG
Fig 12c. Maximum Avalanche Energy Vs. Drain Current
10 V
QGS VG QGD
VGS(th) Gate threshold Voltage (V)
4.0
3.0
Charge
Fig 13a. Basic Gate Charge Waveform
Current Regulator Same Type as D.U.T.
ID = 250A
2.0
50K 12V .2F .3F
D.U.T. VGS
3mA
+ V - DS
1.0 -75 -50 -25 0 25 50 75 100 125 150 175
T J , Temperature ( C )
IG ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
Fig 14. Threshold Voltage Vs. Temperature
6
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IRF1302S/IRF1302L
1000
Duty Cycle = Single Pulse 0.01
Avalanche Current (A)
100
0.05 0.10
10
Allowed avalanche Current vs avalanche pulsewidth, tav assuming Tj = 25C due to avalanche losses
1 1.0E-07 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
Fig 15. Typical Avalanche Current Vs.Pulsewidth
410 360
EAR , Avalanche Energy (mJ)
TOP Single Pulse BOTTOM 10% Duty Cycle ID = 104A
310 260 210 160 110 60 10 25 50 75 100 125 150
Starting T J , Junction Temperature (C)
Notes on Repetitive Avalanche Curves , Figures 15, 16: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 12a, 12b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25C in Figure 15, 16). t av = Average time in avalanche. D = Duty cycle in avalanche = t av *f ZthJC(D, tav) = Transient thermal resistance, see figure 11) PD (ave) = 1/2 ( 1.3*BV*Iav) = DT/ ZthJC Iav = 2DT/ [1.3*BV*Zth] EAS (AR) = PD (ave)*tav
Fig 16. Maximum Avalanche Energy Vs. Temperature
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IRF1302S/IRF1302L
Peak Diode Recovery dv/dt Test Circuit
D.U.T*
+
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
-
+
RG V GS * dv/dt controlled by RG * ISD controlled by Duty Factor "D" * D.U.T. - Device Under Test
+ V DD
*
Reverse Polarity of D.U.T for P-Channel
Driver Gate Drive P.W. Period D=
P.W. Period
[VGS=10V ] ***
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
[VDD]
Re-Applied Voltage Inductor Curent
Body Diode
Forward Drop
Ripple 5%
[ISD]
*** VGS = 5.0V for Logic Level and 3V Drive Devices Fig 17. For N-channel HEXFET(R) power MOSFETs
8
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IRF1302S/IRF1302L
D2Pak Package Outline
D2Pak Part Marking Information
T HIS IS AN IRF530S WIT H LOT CODE 8024 AS S EMBLED ON WW 02, 2000 IN THE AS S EMBLY LINE "L" INT ERNAT IONAL RECTIFIER LOGO AS S EMBLY LOT CODE PART NUMBER F530S DAT E CODE YEAR 0 = 2000 WEEK 02 LINE L
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9
IRF1302S/IRF1302L
TO-262 Package Outline
TO-262 Part Marking Information
EXAMPLE: T HIS IS AN IRL3103L LOT CODE 1789 ASS EMBLED ON WW 19, 1997 IN THE ASS EMBLY LINE "C" INT ERNATIONAL RECTIFIER LOGO AS SEMBLY LOT CODE PART NUMBER
DATE CODE YEAR 7 = 1997 WEEK 19 LINE C
10
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IRF1302S/IRF1302L
D2Pak Tape & Reel Information
TRR
1.60 (.063) 1.50 (.059) 4.10 (.161) 3.90 (.153)
1.60 (.063) 1.50 (.059) 0.368 (.0145) 0.342 (.0135)
FEED DIRECTION 1.85 (.073)
1.65 (.065)
11.60 (.457) 11.40 (.449)
15.42 (.609) 15.22 (.601)
24.30 (.957) 23.90 (.941)
TRL
10.90 (.429) 10.70 (.421) 1.75 (.069) 1.25 (.049) 16.10 (.634) 15.90 (.626) 4.72 (.136) 4.52 (.178)
FEED DIRECTION
13.50 (.532) 12.80 (.504)
27.40 (1.079) 23.90 (.941)
4
330.00 (14.173) MAX.
60.00 (2.362) MIN.
Notes:
NOTES : 1. COMFORMS TO EIA-418. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION MEASURED @ HUB. 4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
26.40 (1.039) 24.40 (.961) 3
30.40 (1.197) MAX. 4
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11). Starting TJ = 25C, L = 0.063mH RG = 25, IAS = 104A. (See Figure 12). ISD 104A, di/dt 100A/s, VDD V(BR)DSS, TJ 175C. Pulse width 400s; duty cycle 2%.
Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS . Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 75A. Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive avalanche performance.
This is applied to D2Pak, when mounted on 1" square PCB ( FR-4 or G-10 Material ).
For recommended footprint and soldering techniques refer to application note #AN-994.
Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR's Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.07/02
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